August 16, 2016, San Francisco—Al Yanes from the PCI-SIG provided an update on the organization its core standards. Although no new capabilities are ready for release, the underlying technologies and standards are showing robust growth.
The organization continues to grow with over 730 member companies now involved. The primary focus is on creating specifications and mechanisms to support compliance and interoperability. The PCIe architecture offers efficient I/O bandwidth per pin and flexible performance through added lanes and varying frequencies. It has the potential to decrease physical footprints through the consolidation of signaling lines.
One current drive is to increase the use of PCI in mobile devices, while efforts continue in other segments like cloud computing and storage, and enterprise servers with version 4.0. In the mobile space, PCI offers up to 16 G transfers per second with version 4.0 and the latest specifications include low power capabilities like L1 sub-state for near zero link idle power, half- and quarter-swing signaling to reduce transfer energy, and high-sped data bursts to reduce overall data transfer duty cycles.
Cloud functions in the specifications include hot-plug support for modules, scalable by lane and frequency, low latency all leading to lower total cost of operations. version 3.0 offered increased numbers of connectors, and version 4.0 continues to offer expansion capabilities. The existing ecosystem contains many types of functions and capabilities to provide a complete infrastructure for large systems. Some functions include PCIe switches and FLASH cards.
PCIe is becoming the leader in storage interconnect. Version 4.0 provides up to 16 GT/s which allows the storage apps to keep data closer to the CPU. Member companies are starting to roll out version 4.0 devices with many expected to start deliveries in Q1 of '17. PCIe storage comes in many form factors including SSDs and plug-in FLASH cards. PCIe switches are used in hybrid storage systems with PCIe-based servers and at the rack level enabling easier use of PCIe SSDs and HDDs.
At the enterprise level, PCIe provides redundancy and failover functions and is becoming ubiquitous as the interconnect. The inclusion of I/O power reduction functions enables dynamic hardware and software power down when no lane traffic is present.
The organization's roadmap to version 5.0 calls for data transfer rates of 25 GT/s through connectors and 32 GT/s in chip-to-chip mode. The next generation will continue to have full back compatibility to all versions from Ver 1.0 through 4.0. Beyond version 5.0, back compatibility may become an issue. The higher data rates raise the question of data integrity, so an optional end-end CRC can be implemented to at least identify transmission errors inherent in the 10^-13 BER of the underlying fabric.
